Stack Height Analysis for FinFET Logic and Circuit
نویسندگان
چکیده
FinFET has appeared to be a good candidate for further extending the technology to the nanoscale regime due to its excellent electrostatic properties and comparative ease of fabrication. Due to little/no body effect in FinFET devices, there is a good chance of increasing the stack height to enable more complex gates and reduce logic depth, which could further improve metrics, like performance. This paper analyzes the tradeoffs between stack height (fan-in) and area/performance through simulating several logic gates based on PTM model. A 64-bit Kogge-Stone adder with different radix size is designed and simulated across five different technology nodes as a case study. The simulation result shows that a radix-4 adder can achieve the best performance, but with area penalty. A design flow that considers all the tradeoffs is also proposed. Keywords—FinFET; stack height; body effect; adder; radix
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